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| Advance Information MPC7455RXLCPNS/D Rev. 0, 1/2003 MPC7455 Part Number Specification for the XPC74x5RXnnnLC Series Motorola Part Numbers Affected: XPC7455RX600LC XPC7455RX733LC XPC7455RX800LC XPC7455RX867LC XPC7455RX933LC PPC7455RX1000LC XPC7445RX600LC XPC7445RX733LC XPC7445RX800LC XPC7445RX867LC XPC7445RX933LC PPC7445RX1000LC This document describes part-number-specific changes to recommended operating conditions and revised electrical specifications, as applicable, from those described in the general MPC7455 RISC Microprocessor Hardware Specifications (Order No. MPC7455EC/D). The devices described in this specification are no longer in production and this document is provided for reference only. For recommended upgrades or replacement devices, contact your Motorola sales office. Specifications provided in this document supersede those in the MPC7455 RISC Microprocessor Hardware Specifications, Rev. 1 or later, for the part numbers listed in Table A only. Specifications not addressed herein are unchanged. Because this document is frequently updated, refer to http://www.motorola.com/semiconductors or to your Motorola sales office for the latest version. Note that headings and table numbers in this document are not consecutively numbered. They are intended to correspond to the heading or table affected in the general hardware specification. Part numbers addressed in this document are listed in Table A. Table A. Part Numbers Addressed by this Data Sheet Operating Conditions Motorola Part Number CPU Frequency (MHz) 600 733 800 867 933 1000 600 733 800 867 933 1000 TJ (C) Significant Differences from Hardware Specification VDD 1.6 V 50 mV XPC7455RX600LC XPC7455RX733LC XPC7455RX800LC XPC7455RX867LC XPC7455RX933LC PPC7455RX1000LC XPC7445RX600LC XPC7445RX733LC XPC7445RX800LC XPC7445RX867LC XPC7445RX933LC PPC7445RX1000LC 0 to 105 Modified core voltage, core and VCO frequency, and power specifications; modified PLL_CFG settings. This document describes all XPC74x5RXnnnLC devices. Rev. 0 of the MPC7455 RISC Microprocessor Hardware Specifications originally described these devices but later revisions of that document describe only later devices. Note: The X prefix in a Motorola part number designates a "Pilot Production Prototype" as defined by Motorola SOP 3-13. These are from a limited production volume of prototypes manufactured, tested, and Q.A. inspected on a qualified technology to simulate normal production. These parts have only preliminary reliability and characterization data. Before pilot production prototypes may be shipped, written authorization from the customer must be on file in the applicable sales office acknowledging the qualification status and the fact that product changes may still occur while shipping pilot production prototypes. 2 MPC7455 Part Number Specification for the XPC74x5RXnnnLC Series MOTOROLA Features 1.1 * Features Power management -- 1.6-V processor core This section summarizes changes to the features of the MPC7455 described in the MPC7455 RISC Microprocessor Hardware Specifications. 1.4 General Parameters * Core power supply: 1.6 V 50 mV DC nominal 1.5.1 DC Electrical Characteristics Table 4 provides the recommended operating conditions for the MPC7455 part numbers described herein. Table 4. Recommended Operating Conditions Characteristic Core supply voltage PLL supply voltage Symbol VDD AVDD Recommended Value 1.6 V 50 mV 1.6 V 50 mV Unit V V Note: These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. MOTOROLA MPC7455 Part Number Specification for the XPC74x5RXnnnLC Series 3 General Parameters Table 7 provides the power consumption for the MPC7455 part numbers described herein. Table 7. Power Consumption for MPC7455 Processor (CPU) Frequency Unit 600 MHz 733 MHz 800 MHz 867 MHz 933 MHz 1 GHz Notes Full-Power Mode Typical Maximum 13.0 17.5 15.6 22.0 17.0 24.0 18.5 26.0 19.9 28.0 21.3 30.0 W W 1, 3 1, 2 Doze Mode Typical -- -- -- Nap Mode Typical 1.4 1.7 1.8 1.9 2.0 2.2 W 1, 3 -- -- -- W 1, 3, 4 Sleep Mode Typical 0.85 0.90 0.90 0.95 1.00 1.00 W 1, 3 Deep Sleep Mode (PLL Disabled) Typical 500 500 510 570 610 640 mW 1, 3 Notes: 1. These values apply for all valid processor bus and L3 bus ratios. The values do not include I/O supply power (OVDD and GVDD) or PLL supply power (AVDD). OVDD and GVDD power is system dependent, but is typically <5% of VDD power. Worst case power consumption for AVDD < 3 mW. 2. Maximum power is measured at nominal VDD (see Table 4) while running an entirely cache-resident, contrived sequence of instructions which keep the execution units, with or without AltiVec, maximally busy. 3. Typical power is an average value measured at the nominal recommended VDD (see Table 4) and 65C in a system while running a typical code sequence. 4. Doze mode is not a user-definable state; it is an intermediate state between Full-Power and either Nap or Sleep mode. As a result, power consumption for this mode is not tested. 4 MPC7455 Part Number Specification for the XPC74x5RXnnnLC Series MOTOROLA General Parameters Table 8 provides the clock AC timing specificatons for the MPC7455 part numbers described herein. Table 8. Clock AC Timing Specifications At recommended operating conditions. See Table 4. Maximum Processor Core Frequency Characteristic Symbol 600 MHz 733 MHz 800 MHz 867 MHz 933 MHz 1 GHz Unit Notes Min Max Min Max Min Max Min Max Min Max Min Max Processor frequency VCO frequency fcore fVCO 500 600 500 733 500 800 500 867 500 933 500 1000 MHz 1 1 1000 1200 1000 1466 1000 1600 1000 1734 1000 1866 1000 2000 MHz Notes: 1. Caution: The SYSCLK frequency, PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies (see Table 4 in the MPC7455 RISC Microprocessor Hardware Specifications). Refer to the PLL_CFG[0:4] signal description in Section 1.9.1, "PLL Configuration," for valid PLL_CFG[0:4] settings. Table 12 provides the L3 bus interface AC timing specifications for MSUG2 for the MPC7455 part numbers described herein. Table 12. L3 Bus Interface AC Timing Specifications for MSUG2 At recommended operating conditions. See Table 4. All Speed Grades Parameter Symbol L2CR[12] = 0 and L3CR[12] = 08 L2CR[12] = 1 and L3CR[12] = 18 Min L3_CLK rise and fall time Setup times: Data and parity Input hold times: Data and parity Valid times: Data and parity Valid times: All other outputs Output hold times: Data and parity Output hold times: All other outputs L3_CLK to high impedance: Data and parity tL3CR, tL3CF tL3DVEH, tL3DVEL -- - 0.1 Max 1.0 -- -- (- tL3_CLK/4) + 0.4 tL3_CLK/4 + 1.0 -- -- tL3_CLK/2 Min -- - 0.1 tL3_ECHO_CLK/4 + 0.6 -- -- tL3_CLK/4 - 0.2 tL3_CLK/4 - 0.3 -- Max 1.0 -- -- (- tL3_CLK/4) + 0.8 tL3_CLK/4 + 1.2 -- -- tL3_CLK/2 ns ns ns ns ns ns ns ns 1 2, 3, 4 2, 4 5, 6, 7 5, 7 5, 6, 7 5, 7 Unit Notes tL3DXEH, tL3_ECHO_CLK/4 tL3DXEL + 0.6 tL3CHDV, tL3CLDV tL3CHOV tL3CHDX, tL3CLDX, tL3CHOX tL3CLDZ -- -- tL3_CLK/4 - 0.4 tL3_CLK/4 - 0.5 -- MOTOROLA MPC7455 Part Number Specification for the XPC74x5RXnnnLC Series 5 General Parameters Table 12. L3 Bus Interface AC Timing Specifications for MSUG2 (continued) At recommended operating conditions. See Table 4. All Speed Grades Parameter Symbol L2CR[12] = 0 and L3CR[12] = 08 L2CR[12] = 1 and L3CR[12] = 18 Min L3_CLK to high impedance: All other outputs tL3CHOZ -- Max tL3_CLK/4 + 2.0 Min -- Max tL3_CLK/4 + 2.0 ns Unit Notes Notes: 1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD. 2. For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising or falling edge of the input L3_ECHO_CLKn (see Figure 10 in the MPC7455 RISC Microprocessor Hardware Specifications). Input timings are measured at the pins. 3. For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in Figure 10 in the MPC7455 RISC Microprocessor Hardware Specifications. For consistency with other input setup time specifications, this will be treated as negative input setup time. 4. tL3_ECHO_CLK/4 is one-fourth the period of L3_ECHO_CLKn. This parameter indicates that the MPC7455 can latch an input signal that is valid for only a short time before and a short time after the midpoint between the rising and falling (or falling and rising) edges of L3_ECHO_CLKn at any frequency. 5. All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the falling) edge of L3_CLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50- load (see Figure 8 in the MPC7455 RISC Microprocessor Hardware Specifications). 6. For DDR, the output data will typically lead the edge of L3_CLKn as shown in Figure 10 in the MPC7455 RISC Microprocessor Hardware Specifications. For consistency with other output valid time specifications, this will be treated as negative output valid time. 7. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched by an internal clock delayed in phase by 90. Therefore, there is a frequency component to the output valid and output hold times such that the specified output signal will be valid for approximately one L3_CLK period starting three-fourths of a clock prior to the edge on which the SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled. 8. These configuration bits allow the AC timing of the L3 interface to be altered via software. They must be both set or both cleared; other configurations will increase tL3CSKW1, which may cause unreliable L3 operation. 6 MPC7455 Part Number Specification for the XPC74x5RXnnnLC Series MOTOROLA General Parameters Table 13 provides the L3 bus AC timing specifications for PB2 and Late Write SRAMs for the MPC7455 part numbers described herein. Table 13. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs At recommended operating conditions. See Table 4. All Speed Grades Parameter Symbol L2CR[12]=0 and L3CR[12]=0 6 Min L3_CLK rise and fall time Setup times: Data and parity Input hold times: Data and parity Valid times: Data and parity Valid times: All other outputs Output hold times: Data and parity Output hold times: All other outputs L3_CLK to high impedance: Data and parity L3_CLK to high impedance: All other outputs tL3CR, tL3CF tL3DVEH tL3DXEH tL3CHDV tL3CHOV tL3CHDX tL3CHOX tL3CHDZ -- 1.5 -- -- -- tL3_CLK/4 - 0.4 tL3_CLK/4 - 0.4 -- Max 1.0 -- 0.5 tL3_CLK/4 + 1.0 tL3_CLK/4 + 1.0 -- -- 2.0 L2CR[12]=1 and L3CR[12]=1 6 Min -- 1.5 -- -- -- tL3_CLK/4 - 0.2 tL3_CLK/4 - 0.2 -- Max 1.0 -- 0.5 tL3_CLK/4 + 1.2 tL3_CLK/4 + 1.2 -- -- 2.0 ns ns ns ns ns ns ns ns 1, 5 2, 5 2, 5 3, 4, 5 4 3, 4, 5 4, 5 5 Unit Notes tL3CHOZ -- 2.0 -- 2.0 ns 5 Notes: 1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD. 2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of the input L3_ECHO_CLKn (see Figure 10 in the MPC7455 RISC Microprocessor Hardware Specifications). Input timings are measured at the pins. 3. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLKn to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50- load (see Figure 10 in the MPC7455 RISC Microprocessor Hardware Specifications). 4. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched by an internal clock delayed in phase by 90. Therefore, there is a frequency component to the output valid and output hold times such that the specified output signal will be valid for approximately one L3_CLK period starting three-fourths of a clock prior to the edge on which the SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled. 5. Timing behavior and characterization are currently being evaluated. 6. These configuration bits allow the AC timing of the L3 interface to be altered via software. They must be both set or both cleared; other configurations will increase tL3CSKW1 and tL3CSKW2, which may cause unreliable L3 operation. MOTOROLA MPC7455 Part Number Specification for the XPC74x5RXnnnLC Series 7 General Parameters 1.9.1 PLL Configuration The MPC7455 PLL is configured by the PLL_CFG[0:4] signals; note that PLL_CFG[4] was formerly called PLL_EXT in earlier documentation. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation. PLL_CFG[4] will normally be pulled low but can be asserted for extended modes of operation. The PLL configuration for the MPC7455 is shown in Table 17 for a set of example frequencies. In this example, shaded cells represent settings that, for a given SYSCLK frequency, result in core and/or VCO frequencies that do not comply with the 1-GHz column in Table 8. Note that the settings for Rev. C devices are different than those for subsequent devices. Table 17. MPC7455 Microprocessor PLL Configuration Example for 1 GHz Parts Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz) PLL_CFG [0:4] Bus-toCore Multiplier 0.5x 2x 2.5x 3x 3.5x 4x 4.5x 5x 5.5x 6x 6.5x 7x 7.5x 8x 9x Core-toVCO Multiplier 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 500 (1000) 533 (1066) 600 (1200) 525 (1050) 563 (1125) 600 (1200) 675 (1350) 540 (1080) 580 (1160) 623 (1245) 664 (1328) 747 (1494) 500 (1000) 550 (1100) 600 (1200) 650 (1300) 700 (1400) 750 (1500) 800 (1600) 900 (1800) 533 (1066) 600 (1200) 667 (1333) 733 (1466) 800 (1600) 866 (1730) 933 (1866) 1000 (2000) Bus 33.3 MHz Bus 50 MHz Bus 66.6 MHz Bus 75 MHz Bus 83 MHz Bus Bus 100 MHz 133 MHz 00000 01000 01100 10000 11100 10100 01110 10110 10010 11010 01010 00100 00010 11000 01111 8 MPC7455 Part Number Specification for the XPC74x5RXnnnLC Series MOTOROLA General Parameters Table 17. MPC7455 Microprocessor PLL Configuration Example for 1 GHz Parts (continued) Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz) PLL_CFG [0:4] Bus-toCore Multiplier 10x 11x 12x 13x 14x 15x 16x Core-toVCO Multiplier 2x 2x 2x 2x 2x 2x 2x 500 (1000) 533 (1066) Bus 33.3 MHz Bus 50 MHz 500 (1000) 550 (1100) 600 (1200) 650 (1300) 700 (1400) 750 (1500) 800 (1600) PLL off, SYSCLK clocks core circuitry directly PLL off, no core clocking occurs Bus 66.6 MHz 667 (1333) 733 (1466) 800 (1600) 865 (1730) 933 (1866) 1000 (2000) Bus 75 MHz 750 (1500) 825 (1650) 900 (1800) 975 (1950) Bus 83 MHz 830 (1660) 913 (1826) 996 (1992) Bus Bus 100 MHz 133 MHz 1000 (2000) 10101 10011 10111 01011 11001 00011 11011 00110 11110 PLL off/bypass PLL off MOTOROLA MPC7455 Part Number Specification for the XPC74x5RXnnnLC Series 9 Ordering Information 1.11 Ordering Information 1.11.1 Part Numbers Addressed by this Specification Table 21 provides the ordering information for the MPC7455 parts described in this document. Table 21. Part Marking Nomenclature XPC Product Code XPC 2 74x5 Part Identifier 7455 7445 RX Package RX = CBGA nnn Processor Frequency 1 600 733 800 867 933 1000 x Application Modifier L: 1.6 V 50 mV 0 to 105C x Revision Level C: 2.1; PVR = 8001 0201 PPC 3 Notes: 1. Processor core frequencies supported by parts addressed by this specification only. Parts addressed by other specifications may support other maximum core frequencies. 2. The X prefix in a Motorola part number designates a "Pilot Production Prototype" as defined by Motorola SOP 3-13. These are from a limited production volume of prototypes manufactured, tested, and Q.A. inspected on a qualified technology to simulate normal production. These parts have only preliminary reliability and characterization data. Before pilot production prototypes may be shipped, written authorization from the customer must be on file in the applicable sales office acknowledging the qualification status and the fact that product changes may still occur while shipping pilot production prototypes. 3. The P prefix in a Motorola part number designates a "Pilot Production Prototype" as defined by Motorola SOP 3-13. These parts have only preliminary reliability and characterization data. Before pilot production prototypes may be shipped, written authorization from the customer must be on file in the applicable sales office acknowledging the qualification status and the fact that product changes may still occur while shipping pilot production prototypes. 10 MPC7455 Part Number Specification for the XPC74x5RXnnnLC Series MOTOROLA Document Revision History 1.11.3 Part Marking Parts are marked as the example shown in Figure 29. XPC7445 RX8000LC MMMMMM ATWLYYWWA XPC7455 RX800LC MMMMMM ATWLYYWWA 7440 BGA 7450 BGA Notes: MMMMMM is the 6-digit mask number. ATWLYYWWA is the traceability code. CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States. Figure 29. Motorola Part Marking for BGA Device Document Revision History Table B provides a revision history for this part number specification. Table B. Document Revision History Rev. No. 0 Initial release. Substantive Change(s) MOTOROLA MPC7455 Part Number Specification for the XPC74x5RXnnnLC Series 11 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-480-768-2130 (800) 521-6274 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre, 2 Dai King Street Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: (800) 521-6274 HOME PAGE: www.motorola.com/semiconductors Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c) Motorola, Inc. 2003 MPC7455RXLCPNS/D |
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